The rising prominence of the RISC-V instruction set architecture has spurred the development of instruction set simulators (ISS), which are crucial for early-stage architecture evaluation and software development. This paper introduces a practical approach to RISC-V ISS using tiered just-in-time (JIT) compilation, a technique commonly employed in high-level language virtual machines but rarely applied to ISS. Our simulator utilizes this strategy to outperform existing open-source simulators in speed and efficiency, quickly executing the initial instruction.

This method incorporates an interpreter for initial execution and profiling, a lightweight tier-1 compiler for moderate enhancements, and an aggressive tier-2 compiler for frequently executed code paths. This balanced approach ensures rapid compilation and detailed refinement, resulting in superior performance across various RISC-V workloads. The paper addresses prevalent challenges in dynamic binary translation, such as indirect jumps and excessive translation times, by introducing innovative solutions and providing an extensive impact analysis.